The so-called gate photon counter was developed in response to the demand for single photon detection in single-spin quantum control experimental research. Single-spin quantum control is to control the defects in the crystal, such as quantum dots and diamond color centers. The signal readout is generally achieved by the detection of a single photon generated by the spin. There are three techniques commonly used in this type of experiment: gate photon counting, timing counting, and correlation function measurement. The system described in this article establishes a scalable communication and control architecture that can add counting functions in different ways.
1 System structure design
The schematic diagram of the overall system structure is shown in Figure 1. Data communication and command transmission with the counting system are realized through the Ethernet port of the PC. The PC sends commands such as the selection of working mode to the system through the network port, and the system will be in different modes The data such as the count value and count status are sent to the PC through the network port, and the data is processed by the PC. The main chip of the system uses XC3S500E of Xilinx's SPARTAN 3E series. The photon counting input of the system is introduced by two BNC interfaces. These two interfaces can be configured by FPGA to make the photon counter work in different modes. The firmware of the system is programmed in the FLASH chip, and SDRAM provides a large-capacity storage space for loading Microblaze soft-core code, counting application code, and storing counted data at runtime.
The system uses FPGA as the processing center to realize various working modes. Its functional block diagram is shown in Figure 2. The functional modules mainly include the soft core Microblaze, the interface to external memory MPMC, and the Counterpulse IP core that needs to be designed and implemented. Between the Counterpulse IP core and the processor soft core, the FSL bus is used for connection to realize the configuration of the Counterpu-lse core by Microbalze and the data transmission from the Counterpulse core to Microblaze.
When the system is working, the Microblaze soft core receives the command sent by the PC through the network port, and according to the command, the photon counting IP core is selected and configured through the FSL bus. The counting IP core counts the external counting source. The counting results and status data are sent to the Microblaze soft core through another FSL bus. The Microblaze soft core buffers the data in the DDRRAM and sends the data to the PC through the network port. Machine, analyzed and processed by PC.
The system has three working modes: mode one: enable counting, when the enable signal is valid (high level effective), count the count pulse signal input by the photon counting; mode two: constant cycle counting, according to the set counting cycle, Count the count pulse signal of the photon counting input; Mode three: Separate timing of start and stop signals, according to the input count start signal and count stop signal (both rising edge valid), time based on the system fundamental frequency, To achieve function measurement.
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