The STM32 microcontroller is equipped with a powerful exception handling system based on the Cortex-M core. This system categorizes events that can interrupt the normal execution of code into two types: exceptions and interrupts. Exceptions are internal events managed by the kernel, while interrupts are external signals that can be handled by the system. These are organized in a table known as the interrupt vector table, which starts from index 0 to 15 for kernel exceptions and begins at index 16 for external interrupts.
In STM32, the vector table is reorganized such that interrupts numbered from -3 to 6 are classified as system exceptions, including critical events like reset, non-maskable interrupts (NMI), and hard faults. These cannot be prioritized or masked. Starting from index 7, the interrupts are considered external, and their priorities can be configured by the user.
With so many possible interrupts in STM32, manually configuring them would be complex and error-prone. To simplify this process, the Nested Vectored Interrupt Controller (NVIC) is used. The NVIC is an integral part of the Cortex-M core and provides efficient control over interrupt priorities and configurations.
To configure an interrupt in STM32, there are two main concepts to understand: preemption priority and response priority. Preemption priority determines whether an interrupt can interrupt another ongoing interrupt service routine (ISR). A lower numerical value indicates a higher priority. If two interrupts have the same preemption priority, the response priority comes into play, determining which one is handled first when both occur simultaneously.
The number of bits allocated to preemption and response priorities depends on the priority grouping configuration. For example:
- **Group 0**: All 4 bits are used for preemption priority (16 levels).
- **Group 1**: 1 bit for preemption, 3 bits for response (2 preemption levels, 8 response levels).
- **Group 2**: 2 bits for preemption, 2 bits for response (4 preemption levels, 4 response levels).
- **Group 3**: 3 bits for preemption, 1 bit for response (8 preemption levels, 2 response levels).
- **Group 4**: All 4 bits are used for response priority (16 response levels).
The configuration process involves several steps:
1. Define an interrupt configuration structure variable.
```c
NVIC_InitTypeDef NVIC_InitStruct;
```
2. Set the priority grouping using `NVIC_PriorityGroupConfig()`.
3. Configure the interrupt parameters:
- `NVIC_InitStruct.NVIC_IRQChannel`: Specify the interrupt source.
- `NVIC_InitStruct.NVIC_IRQChannelCmd`: Enable or disable the interrupt.
- `NVIC_InitStruct.NVIC_IRQChannelPreemptionPriority`: Set the preemption priority.
- `NVIC_InitStruct.NVIC_IRQChannelSubPriority`: Set the response priority.
4. Initialize the NVIC with `NVIC_Init(&NVIC_InitStruct)`.
This structured approach ensures that interrupts are handled efficiently and in the correct order, making it easier to manage complex embedded systems.
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