The PHY1068 is an active equalizer and retiming with greatly extended, programmable pre-emphasis designed for 8.5Gbps backplane applications. The device integrates a stage of automatic input gain control, making noise-sensitive limited connections inadequate, and its powerful equalizer means that it can extract typical data from the signal to degenerate or reflect the backplane environment.
The high degree of integration reduces the required board area and firmware development, minimizing cost and time-to-market complexity. The output driver on the programmable pre-emphasis device provides the PHY1068 to be used in a variety of applications.
Manufactured in an advanced CMOS process, PHY1068 is packaged in a RoHS-compliant, 36-ball BGA package.
Key features
Optimize 8.5G Fibre Channel
Fully integrated equalizer and phase algorithm to minimize firmware development
Low latency (15ns)
User programmable pre-emphasis driver
Integrated PRBS and system design verification test and BERT test
Lost signal (LOS) and lost lock (laughs) alarm
Automatic detection of 2-wire interface or SPI â„¢ microcontroller
Small size, adopts 5mm x 5mm package 36 ball BGA and ball spacing is 0.8mm
Minimal external component requirements
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