**1 Introduction**
The GaAs MMIC control circuit has become a key component in various electronic systems due to its compact size, lightweight, fast switching speed, radiation resistance, high reliability, and minimal power consumption. In modern advanced mobile communication systems—such as space diversity smart antennas and phased array systems—amplitude and phase adjustments are essential. When it comes to phase adjustment, the smaller the amplitude, the better. Similarly, when adjusting amplitude, the phase change should be as minimal as possible. The paper introduces a DC-50 GHz ultra-wideband GaAs MMIC voltage-controlled E-attenuator, which features a low dynamic insertion range, excellent linearity in attenuation with respect to control voltage variation, superior input/output standing wave performance, and multiple functionalities. Among these, the low insertion phase shift is its most prominent feature.
This circuit can be applied in several ways:
a) As a DC-50 GHz MMIC variable attenuator with low insertion phase shift, it can serve as an automatic loss control component;
b) In a multi-octave vector modulator, it can perform amplitude modulation and adjustment while introducing minimal phase shift;
c) It can function as a high-performance absorption (or matching) single-pole single-throw switch at DC-50 GHz;
d) It can act as a multi-octave pulse amplitude modulator;
e) It can be cascaded with a wideband amplifier to form an AGC (Automatic Gain Control) amplifier that offers a wide frequency band, large dynamic range, and high linearity in attenuation relative to control voltage.
**2 Design**
The overall design and implementation of this monolithic voltage-controlled variable attenuator involve several key steps. First, based on the required electrical performance specifications, an appropriate circuit topology is selected, and a reasonable switch MESFET is designed. Next, an equivalent circuit model parameter scaling equation for the switching MESFET is derived across the DC-50 GHz frequency range. To simplify the circuit and reduce power consumption, load design methods such as series and parallel switch MESFETs with two control terminals are employed.
Since the circuit operates using complementary control voltages that manage the series and parallel switching MESFETs, the loads on both control terminals must be balanced during the ESC (electronic switch control) process. Otherwise, the standing wave characteristics may be significantly degraded. To address this, the DC parameter circuit is typically designed to balance the loads of the two control terminals, thereby improving the standing wave characteristics during ESC control.
In this paper, the same method of selecting two control loads during design is used to enhance the standing wave characteristics at the ESC control terminal. The process includes: simulating and optimizing the circuit using mature microwave monolithic design software like AgilentEesof; performing layout design based on the optimization results; conducting secondary simulations and optimizations according to the layout design; selecting and designing a suitable process route; and finally, executing the microwave test in the film.
The circuit principle is illustrated in Figure 1. A wideband switching circuit topology with a matched SPST (Single-Pole Single-Throw) configuration is adopted. The two ends of the switching arm are connected to an absorption resistor and a parallel branch of the switch MESFET, while multiple switch MESFETs are connected in parallel with the main transmission path. Low-dispersion, wideband coplanar waveguide transmission lines are used to broaden the frequency bandwidth.
The basic principle behind the low-insertion phase shift function is phase cancellation. This means that the phase lag introduced by the series branch inductive reactance is canceled out by the phase lead from the parallel branch capacitive reactance. Key electrical performance indicators considered in the design include: a frequency range from DC to 50 GHz, minimal attenuation within the band, low input/output standing waves at minimum attenuation, maximum attenuation with good flatness, low input/output standing waves at maximum attenuation, and a low phase shift with minimal attenuation phase shift ratio.
To achieve optimal electrical performance, different MESFETs require different optimal gate widths. Therefore, the model parameter scaling technique is used in the design. Circuit model parameters are extracted using HPIC-CAP software and the corresponding model parameter extraction system. Due to the high-frequency design up to 50 GHz, frequency expansion and fitting techniques are also applied to obtain the design parameters for the DC-50 GHz switching MESFET circuit model.
**3 Fabrication**
The chip is fabricated using the ion implantation wafer process line at the Nanjing Electronics Research Institute. This process ensures a high yield and long-term stability. The fabrication process includes Au/Ge/Ni ohmic contact metallization, a 0.5 μm gate length Ti/Pt/Au Schottky barrier gate, N+ and N- implantation, ion implantation resistance, metal film resistance, SiO2 passivation film, air bridge, through-hole grounding, back metallization, and plating. The process yield is over 80%, and the electrical properties of the chips match well with those of the wafers. The chip dimensions are 2.33 mm × 0.68 mm × 0.1 mm. The chip photo is shown in Figure 2. The signal input/output terminals use coplanar waveguide interfaces with through-hole grounding and multi-chip passivation technology, ensuring high reliability. All control terminals are located on one side of the chip for easy installation and use.
**4 Performance**
Electrical performance testing was conducted using a microwave on-chip test system consisting of an HP8510C vector network analyzer and a Cascade Microtech microwave probe station. Various parameters were measured, including minimum attenuation, input/output standing waves at minimum attenuation, maximum attenuation, input/output standing waves at maximum attenuation, and the phase shift difference between minimum and maximum attenuation states.
When V1 is 0V and V2 is at the negative FET pinch-off voltage VP, the circuit is in the minimum attenuation state. Conversely, when V1 is at VP and V2 is 0V, it is in the maximum attenuation state. As V1 gradually decreases from 0V to VP, and V2 increases from VP to 0V, the attenuation level transitions from minimum to maximum. The chip has passed rigorous environmental tests, including high and low temperature storage, high and low temperature impact, high and low temperature operation, bonding, shearing, and a 1000-hour working life at 125°C.
**5 Conclusion**
The successful development of a low-phase-shift, multi-functional DC-50 GHz high-performance MMIC voltage-controlled variable attenuator demonstrates excellent electrical performance, high process yield, and high reliability. It meets the design requirements and holds significant practical value in modern communication systems.
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