At present, the GSM system remains one of the most widely adopted mobile communication standards globally. The RF front-end architecture in GSM systems typically involves a combination of a GSM/DCS dual-band power amplifier module and a single-pole four-throw (SP4T) RF switch module. The GSM/DCS dual-band power amplifier integrates a single RF power amplifier die that supports both GSM and DCS frequency bands, along with input-output matching networks and a CMOS controller, all packaged into a single chip. This configuration enables efficient dual-band operation. Meanwhile, the SP4T RF switch module combines a GSM/DCS dual-band filter with an SP4T switch die to manage signal routing effectively.
This paper introduces a novel RF power amplifier circuit designed to achieve dual-band amplification for GSM and DCS. RADICO has implemented this design. The RF power amplifier die has been reduced from two to one, and key components such as the RF power amplifier, output matching network, CMOS controller, and RF switch have been integrated into a single chip module, forming a compact GSM/DCS dual-band RF front-end module, as illustrated in Figure 1.
**Single Chip Amplifier Circuit**
The RF power amplifier circuit in this design employs a three-stage amplification structure. As shown in Figure 2, the first stage is divided into two separate inputs, each dedicated to either the GSM or DCS band. The second and third stages are shared between the two bands. An output matching network capable of handling both GSM and DCS frequencies is implemented at the final stage. Because the second and third stages serve both frequency bands, the design must accommodate the requirements of both GSM and DCS simultaneously.
The third stage of the circuit functions as the power amplifier stage. Under normal battery voltage conditions, the output impedance for both the GSM and DCS bands is set to 2 Ω, allowing for output powers of 35 dBm and 33 dBm, respectively. Since the GSM band requires higher output power, the maximum output power of the third-stage transistor Q3 is designed to reach 35 dBm.
The second stage acts as the driver stage and must cover both GSM and DCS frequency bands, which necessitates a wide operating frequency range. To achieve this, a negative feedback structure is used in the second stage to extend the operational bandwidth. Additionally, the inter-stage matching networks between the second and third stages are designed as broadband matching networks. The combined gain of the second and third stages is set to 25 dB, covering both GSM and DCS bands. The simulation results are presented in Figure 3.
Due to the slightly lower gain in the high-frequency DCS band, the first stage gain for the DCS band is designed to be approximately 3 dB higher than that for the GSM band. A filter network is also added to the RF input of the DCS band, as shown in Figure 2. This network acts as a band-stop filter for the GSM band and a band-pass filter for the DCS band, significantly improving cross-isolation. The simulation schematic and results of the filter network are shown in Figures 4 and 5, respectively. The total gain performance for both the GSM and DCS bands is presented in Figures 6 and 7.
Characristic
â—High permeability
â—Low loss
â—Magnetostriction coefficient is close to zero
â—Curie temperature is high
Application fields
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