A Novel RF Power Amplifier Circuit Design

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At present, the GSM system remains one of the most widely adopted mobile communication standards globally. The RF front-end architecture in GSM systems typically consists of a combination of a GSM/DCS dual-band power amplifier module and a single-pole four-throw (SP4T) RF switch module. The dual-band power amplifier integrates a single RF power amplifier die capable of handling both GSM and DCS frequency bands, along with input-output matching networks and a CMOS controller, all packaged into a single chip. This design enables efficient dual-band operation. Meanwhile, the SP4T RF switch module combines a GSM/DCS dual-band filter with an SP4T switch die to manage signal routing effectively. This paper introduces a novel RF power amplifier circuit that achieves dual-band amplification for both GSM and DCS using a single RF power amplifier die. RADICO utilizes this innovative structure, reducing the number of RF power amplifier dies from two to one. Moreover, the RF power amplifier, output matching network, CMOS controller, and RF switch are integrated into a single chip module, forming a compact GSM/DCS dual-band RF front-end module, as illustrated in Figure 1. **Single Chip Amplifier Circuit** The RF power amplifier in this design employs a three-stage configuration. As shown in Figure 2, the first stage is divided into two separate inputs, each dedicated to the respective GSM and DCS frequency bands. The second and third stages are shared between the two bands. An output matching network compatible with both GSM and DCS is implemented at the final stage. Since the second and third stages serve both frequency bands, the design must account for the requirements of both GSM and DCS simultaneously. The third stage functions as the power amplifier stage. Under normal battery voltage conditions, the output impedance for the GSM band is designed to be 2 Ω, while for the DCS band it is 3 Ω. This setup allows the GSM band to achieve a power output of 35 dBm, and the DCS band to reach 33 dBm. Given that the GSM band requires higher output power, the maximum output power of the third-stage transistor Q3 is set to 35 dBm. The second stage serves as the power driver stage, covering both GSM and DCS frequency bands. Due to the wide frequency range, a negative feedback structure is employed to extend the operating bandwidth. Additionally, the inter-stage matching networks between the second and third stages are designed as broadband matching networks. The total gain of the second and third stages is set to 25 dB, covering both GSM and DCS bands. The simulation results are presented in Figure 3. Because the gain for the high-frequency DCS band is slightly lower in the second and third stages, the first stage gain for the DCS band is designed to be approximately 3 dB higher than that for the GSM band. A filter network is also added to the DCS band’s RF input, as depicted in Figure 2. This network acts as a band-stop filter for the GSM band and a band-pass filter for the DCS band, significantly improving cross-isolation. The simulation schematic and results of the filter network are shown in Figures 4 and 5, respectively. The overall gain performance for both the GSM and DCS bands is illustrated in Figures 6 and 7.

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